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www.irf.com 1 afl28xxd series the afl series of dc/dc converters feature high power density with no derating over the full military temperature range. this series is offered as part of a complete family of converters providing single and dual output voltages and operating from nominal +28v or +270v inputs with output power ranging from 80w to 120w. for applications requiring higher output power, individual converters can be operated in parallel. the internal current sharing circuits assure equal current distribution among the paralleled converters. this series incorporates international rectifier?s proprietary magnetic pulse feedback technology providing optimum dynamic line and load regulation response. this feedback system samples the output voltage at the pulse width modulator fixed clock frequency, nominally 550khz. multiple converters can be synchronized to a system clock in the 500khz to 700khz range or to the synchronization output of one converter. undervoltage lockout, primary and secondary referenced inhibit, soft-start and load fault protection are provided on all models. description 16v to 40v input range 5v, 12v, and 15v outputs available high power density - up to 70w/in 3 up to 100w output power parallel operation with power sharing low profile (0.380") seam welded package ceramic feedthru copper core pins high efficiency - to 87% full military temperature range continuous short circuit and overload protection output voltage trim primary and secondary referenced inhibit functions line rejection > 40db - dc to 50khz external synchronization port fault tolerant design single output versions available standard microcircuit drawings available features afl 28v input, dual output manufactured in a facility fully qualified to mil-prf- 38534, these converters are fabricated utilizing dscc qualified processes. for available screening options, refer to device screening table in the data sheet. variations in electrical, mechanical and screening can be accommodated. contact ir santa clara for special requirements. these converters are hermetically packaged in two enclosure variations, utilizing copper core pins to minimize resistive dc losses. three lead styles are available, each fabricated with international rectifier?s rugged ceramic lead-to-package seal assuring long term hermeticity in the most harsh environments. hybrid-high reliability dc/dc converter pd-94458c
2 www.irf.com afl28xxd series specifications static characteristics -55c < t case < +125c, 16v < v in < 40v unless otherwise specified. for notes to specifications, refer to page 4 input voltage -0.5v to +50vdc soldering temperature 300c for 10 seconds operating case temperature -55c to +125c storage case temperature -65c to +135c absolute maximum ratings parameter group a subgroups test conditions min nom max unit input voltage note 6 16 28 40 v output voltage afl2805d afl2812d afl2815d afl2805d afl2812d afl2815d 1 1 1 1 1 1 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 v in = 28 volts, 100% load positive output negative output positive output negative output positive output negative output positive output negative output positive output negative output positive output negative output 4.95 -5.05 11.88 -12.12 14.85 -15.15 4.90 -5.10 11.76 -12.24 14.70 -15.30 5.00 -5.00 12.00 -12.00 15.00 -15.00 5.05 -4.95 12.12 -11.88 15.15 -14.85 5.10 -4.90 12.24 -11.76 15.30 -14.70 v output current afl2805d afl2812d afl2815d v in = 16, 28, 40 volts - notes 6, 11 either output either output either output 12.8 6.4 5.3 a output power afl2805d afl2812d afl2815d total of both outputs. notes 6,11 80 96 100 w maximum capacitive load each output note 1 10,000 f output voltage temperature coefficient v in = 28 volts, 100% load - notes 1, 6 -0.015 +0.015 %/c output voltage regulation line load cross afl2805d afl2812d afl2815d 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 note 10 no load, 50% load, 100% load v in = 16, 28, 40 volts. v in = 16, 28, 40 volts. note 12 positive output negative output positive output negative output positive output negative output -0.5 -1.0 -1.0 -8.0 -1.0 -5.0 -1.0 -5.0 +0.5 +1.0 +1.0 +8.0 +1.0 +5.0 +1.0 +5.0 %
www.irf.com 3 afl28xxd series static characteristics (continued) for notes to specifications, refer to page 4 parameter group a subgroups test conditions min nom max unit output ripple voltage afl2805d afl2812d afl2815d 1, 2, 3 1, 2, 3 1, 2, 3 v in = 16, 28, 40 volts, 100% load, bw = 10mhz 60 80 80 mv pp input current no load inhibit 1 inhibit 2 afl2805d afl2812d, 15d 1 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 v in = 28 volts i out = 0 pin 4 shorted to pin 2 pin 12 shorted to pin 8 80 100 5.0 50 30 ma input ripple current afl2805d afl2812d afl2815d 1, 2, 3 1, 2, 3 1, 2, 3 v in = 28 volts, 100% load 60 60 60 ma pp current limit point expressed as a percentage of full rated load 1 2 3 v out = 90% v nom , equal current on positive and negative outputs. note 5 115 105 125 125 115 140 % load fault power dissipation overload or short circuit 1, 2, 3 v in = 28 volts 33 w efficiency afl2805d afl2812d afl2815d 1, 2, 3 1, 2, 3 1, 2, 3 v in = 28 volts, 100% load 78 82 81 81 84 85 % enable inputs (inhibit function) converter off sink current converter on sink current 1, 2, 3 1, 2, 3 logical low on pin 4 or pin 12 note 1 logical high on pin 4 and pin 12 - note 9 note 1 -0.5 2.0 0.8 100 50 100 v a v a switching frequency 1, 2, 3 500 550 600 khz synchronization input frequency range pulse amplitude, hi pulse amplitude, lo pulse rise time pulse duty cycle 1, 2, 3 1, 2, 3 1, 2, 3 note 1 note 1 500 2.0 -0.5 20 700 10 0.8 100 80 khz v v ns % isolation 1 input to output or any pin to case (except pin 3). test @ 500vdc 100 m ? device weight slight variations with case style 85 g mtbf mil-hdbk-217f, aif @ t c = 70c 300 khrs
4 www.irf.com afl28xxd series dynamic characteristics -55c < t case < +125c, v in =28v unless otherwise specified. notes to specifications: 1. parameters not 100% tested but are guaranteed to the limits specified in the table. 2. recovery time is measured from the initiation of the transient to where v out has returned to within 1.0% of v out at 50% load. 3. line transient transition time 100 s. 4. turn-on delay is measured with an input voltage rise time of between 100v and 500v per millisecond. 5. current limit point is that condition of excess load causing output voltage to drop to 90% of nominal. 6. parameter verified as part of another test. 7. all electrical tests are performed with the remote sense leads connected to the output leads at the load. 8. load transient transition time 10 s. 9. enable inputs internally pulled high. nominal open circuit voltage 4.0vdc. 10. load current split equally between +v out and -v out . 11. output load must be distributed so that a minimum of 20% of the total output power is being provided by one of the outputs. 12. cross regulation measured with load on tested output at 20% of maximum load while changing the load on other output from 20% to 80%. parameter group a subgroups test conditions min nom max unit load transient response afl2805d amplitude either output recovery amplitude recovery afl2812d amplitude either output recovery amplitude recovery afl2815d amplitude either output recovery amplitude recovery 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 4, 5, 6 note 2, 8 load step 50% ? 100% load step 10% ? 50% 10% ? 50% 50% ? 10% load step 50% ? 100% load step 10% ? 50% 10% ? 50% 50% ? 10% load step 50% ? 100% load step 10% ? 50% 10% ? 50% 50% ? 10% -450 -450 -750 -750 -750 -750 450 200 450 200 400 750 200 750 200 400 750 200 750 200 400 mv s mv s s mv s mv s s mv s mv s s line transient response amplitude recovery note 1, 2, 3 v in step = 16 ? 40 volts -500 500 500 mv s turn-on characteristics overshoot delay 4, 5, 6 4, 5, 6 v in = 16, 28, 40 volts. note 4 enable 1, 2 on. (pins 4, 12 high or open) 0 4.0 250 10 mv ms load fault recovery same as turn on characteristics. line rejection mil-std-461d, cs101, 30hz to 50khz note 1 40 50 db
www.irf.com 5 afl28xxd series block diagram figure ii. enable input equivalent circuit circuit operation and application information the afl series of converters employ a forward switched mode converter topology. (refer to the block diagram in figure i.) operation of the device is initiated when a dc voltage whose magnitude is within the specified input voltage limits is applied between pins 1 and 2. if pin 4 is enabled (at a logical 1 or open) the primary bias supply will begin generating a regulated housekeeping voltage bringing the circuitry on the primary side of the converter to life. a power mosfet is used to chop the dc input voltage into a high frequency square wave, applying this chopped voltage to the power transformer at the nominal converter switching frequency. by maintaining a dc voltage within specified operating range at the input, continuous generation of the bias voltage is assured. the switched voltage impressed on the secondary output transformer windings is rectified and filtered to provide the positive and negative converter output voltages. an error amplifier on the secondary side compares the positive output voltage to a precision reference and generates an error signal proportional to the difference. this error signal is magnetically coupled through the feedback transformer into the control section of the converter varying the pulse width of the square wave signal driving the mosfets, narrowing the pulse width if the output voltage is too high and widening it if it is too low. these pulse width variations provide the necessary corrections to regulate the magnitude of output voltage within its? specified limits. because the primary portion of the circuit is coupled to the secondary side with magnetic elements, full isolation from input to output is maintained. although incorporating several sophisticated and useful ancilliary features, basic operation of the afl28xxd series series can be initiated by simply applying an input voltage to pins 1 and 2 and connecting the appropriate loads between pins 7, 8, and 9. as is the case with any high power density converter, operation should not be initiated before secure attachment to an appropriate heat dissipator. (see thermal considerations, page 7) additional application information is provided in the paragraphs following. inhibiting converter output (enable) as an alternative to application and removal of the dc voltage to the input, the user can control the converter output by providing ttl compatible, positive logic signals to either of two enable pins (pin 4 or 12). the distinction between these two signal ports is that enable 1 (pin 4) is referenced to the input return (pin 2) while enable 2 (pin 12) is referenced to the output return (pin 8). thus, the user has access to an inhibit function on either side of the isolation barrier. each port is internally pulled ?high? so that when not used, an open connection on both enable pins permits normal converter operation. when their use is desired, a logical ?low? on either port will shut the converter down. pin 4 or pin 12 1n4148 100k 200k 220k 2n3904 +5.6v disable pin 2 or pin 8 + input enable 1 input filter sync input primary bias supply control sync output input return case 4 1 5 6 3 2 error amp & ref output filter current sense output filter share amplifier + output output return -output share enable 2 output voltage trim 7 8 9 11 12 10 figure i. dual output
6 www.irf.com afl28xxd series figure iii. preferred connection for parallel operation synchronization of multiple converters parallel operation-current and stress sharing internally, these ports differ slightly in their function. in use, a low on enable 1 completely shuts down all circuits in the converter, while a low on enable 2 shuts down the secondary side while altering the controller duty cycle to near zero. externally, the use of either port is transparent to the user save for minor differences in idle current. (see specification table). when operating multiple converters, system requirements often dictate operation of the converters at a common frequency. to accommodate this requirement, the afl series converters provide both a synchronization input and output. the sync input port permits synchronization of an afl connverter to any compatible external frequency source operating between 500khz and 700khz. this input signal should be referenced to the input return and have a 10% to 90% duty cycle. compatibility requires transition times less than 100ns, maximum low level of +0.8v and a minimumigh level of +2.0v. the sync output of another converter which has been designated as the master oscillator provides a convenient frequency source for this mode of operation. when external synchronization is not indicted, the sync in pin should be left open (unconnected) thereby permitting the converter to operate at its? own internally set frequency. the sync output signal is a continuous pulse train set at 550 50khz, with a duty cycle of 15 5%. this signal is referenced to the input return and has been tailored to be compatible with the afl sync input port. transition times are less than 100ns and the low level output impedance is less than 50 ? . this signal is active when the dc input voltage is within the specified operating range and the converter is not inhibited. this synch output has adequate drive reserve to synchronize at least five additional converters. a typical synchronization connection option is illustrated in figure iii. power input (other converters) share bus 1 6 afl 7 12 - output enable 2 + output return trim share vin rtn case enable 1 sync out sync in 1 6 afl 7 12 - output enable 2 + output return trim share vin rtn case enable 1 sync out sync in 1 6 afl 7 12 - output enable 2 + output return trim share vin rtn case enable 1 sync out sync in optional synchronization connection to positive load to negative load figure iii. illustrates the preferred connection scheme for operation of a set of afl converters with outputs operating in parallel. use of this connection permits equal current sharing among the members of a set whose load current exceeds the capacity of an individual afl. an important feature of the afl series operating in the parallel mode is that in addition to sharing the current, the stress induced by temperature will also be shared. thus if one member of a paralleled set is operating at a higher case temperature, the current it provides to the load will be reduced as compensation for the temperature induced stress on that device.
www.irf.com 7 afl28xxd series a conservative aid to estimating the total heat sink surface area (a heat sink ) required to set the maximum case temperature rise ( ? t) above ambient temperature is given by the following expression: a heat sink ? ? ? ? ? ? ? ? ? t p 80 30 085 143 . . . where ? t pp eff out = ==? ? ? ? ? ? ? case temperature rise above ambient device dissipation in watts 1 1 ? t = 85 - 25 = 60c and the required heat sink area is from the specification table, the worst case full load efficiency for afl2815d is 83% at 100w: thus, power dissipation at full load is given by because of the incorporation of many innovative technological concepts, the afl series of converters is capable of providing very high output power from a package of very small volume. these magnitudes of power density can only be obtained by combining high circuit efficiency with effective methods of heat removal from the die junctions. this requirement has been effectively addressed inside the device; but when operating at maximum loads, a significant amount of heat will be generated and this heat must be conducted away from the case. to maintain the case temperature at or below the specified maximum of 125c, this heat must be transferred by conduction to an appropriate heat dissipater held in intimate contact with the converter base-plate. when operating in the shared mode, it is important that symmetry of connection be maintained as an assurance of optimum load sharing performance. thus, converter outputs should be connected to the load with equal lengths of wire of the same gauge and should be connected to a common physical point, preferably at the load along with the converter output and return leads. all converters in a paralleled set must have their share pins connected together. this arrangement is diagrammatically illustrated in figure iii. showing the output and return pins connected at a star point which is located close as possible to the load. as a consequence of the topology utilized in the current sharing circuit, the share pin may be used for other functions. in applications requiring only a single converter, the voltage appearing on the share pin may be used as a ?total current monitor?. the share pin open circuit voltage is nominally +1.00v at no load and increases linearly with increasing total output current to +2.20v at full load. note that the current we refer to here is the total output current, that is, the sum of the positive and negative outout currents. 1 sil-pad is a registered trade mark of bergquist, minneapolis, mn thermal considerations since the effectiveness of this heat transfer is dependent on the intimacy of the baseplate/heatsink interface, it is strongly recommended that a high thermal conductivity heat transferring medium is inserted between the baseplate and heatsink. the material most frequently utilized at the factory during all testing and burn-in processes is sold under the trade name of sil-pad ? 400 1 . this particular product is an insulator but electrically conductive versions are also available. use of these materials assures maximum surface contact with the heat dissipater thereby compensating for any minor surface variations. while other available types of heat conductive materials and thermal compounds provide similar effectiveness, these alternatives are often less convenient and can be somewhat messy to use. as an example, assume that it is desired to operate an afl2815d in a still air environment where the ambient temperature is held to a constant +25c while holding the case temperature at t c +85c; then case temperature rise is () p =? ? ? ? ? ? ? ? =? = 100 1 83 1 100 0 205 20 5 . ..w a = 60 80 20.5 in heat sink 0.85 ? ? ? ? ? ? ? ?= ? 143 2 30 563 . .. thus, a total heat sink surface area (including fins, if any) of 56 in 2 in this example, would limit case rise to 60c above ambient. a flat aluminum plate, 0.25" thick and of approximate dimension 4" by 7" (28 in 2 per side) would suffice for this application in a still air environment. note that to meet the criteria in this example, both sides of the plate require unrestricted exposure to the +25c ambient air.
8 www.irf.com afl28xxd series general application information the afl28xxd series of converters are capable of providing large transient currents to user loads on demand. because the nominal input voltage range in this series is relatively low, the resulting input current demands will be correspondingly large. it is important therefore, that the line impedance be kept very low to prevent steady state and transient input currents from degrading the supply voltage between the voltage source and the converter input. in applications requiring high static currents and large transients, it is recommended that the input leads be made of adequate size to minimize resistive losses, and that a good quality capacitor of approximately 100 fd be connected directly across the input terminals to assure an adequately low impedance at the input terminals. table i relates nominal resistance values and selected wire sizes. figure v. connection for v out adjustment input filter undervoltage lockout the afl28xxd series converters incorporate a two stage lc input filter whose elements dominate the input load impedance characteristic during the turn-on sequence. the input circuit is as shown in figure iv. figure iv. input filter circuit a minimum voltage is required at the input of the converter to initiate operation. this voltage is set to 14v 0.5v. to preclude the possibility of noise or other variations at the input falsely initiating and halting converter operation, a hysteresis of approximately 1.0v is incorporated in this circuit. thus if the input voltage droops to 13v 0.5v, the converter will shut down and remain inoperative until the input voltage returns to 14v. output voltage adjust connect r adj to + to increase, - to decrease pin 1 pin 2 900nh 130nh 6 fd 11.2 fd by use of the trim pin (10), the magnitude of output voltages can be adjusted over a limited range in either a positive or negative direction. connecting a resistor between the trim pin and either the output return or the positive output will raise or lower the magnitude of output voltages. the span of output voltage adjustment is restricted to the limits shown in table i. enable 2 share trim - vout return + vout to loads r adj afl28xxd 7 12 + - table 1. output voltage trim values and limits afl2805d afl2812d afl2815d v out r adj v out r adj v out r adj 5.5 0 12.5 0 15.5 0 5.4 12.5k 12.4 47.5k 15.4 62.5k 5.3 33.3k 12.3 127k 15.3 167k 5.2 75k 12.2 285k 15.2 375k 5.1 200k 12.1 760k 15.1 1.0m 5.0 12.0 15.0 4.9 190k 11.7 975k 14.6 1.2m 4.8 65k 11.3 288k 14.0 325k 4.7 23k 10.8 72.9k 13.5 117k 4.6 2.5k 10.6 29.9k 13.0 12.5k 4.583 0 10.417 0 12.917 0 note that the nominal magnitude of output voltage resides in the middle of the table and the corresponding resistor value is set to . to set the magnitude greater than nominal, the adjust resistor is connected to output return. to set the magnitude less than nominal, the adjust resistor is connected to the positive output. (refer to figure v.) for output voltage settings that are within the limits, but between those listed in table i, it is suggested that the resistor values be determined empirically by selection or by use of a variable resistor. the value thus determined can then be replaced with a good quality fixed resistor for permanent installation. when use of this adjust feature is elected, the user should be aware that the temperature performance of the converter output voltage will be affected by the temperature performance of the resistor selected as the adjustment element and therefore, is advised to employ resistors with a tight temperature coefficient of resistance.
www.irf.com 9 afl28xxd series table 2. nominal resistance of cu wire wire size, awg resistance per ft 24 ga 25.7 m ? 22 ga 16.2 m ? 20 ga 10.1 m ? 18 ga 6.4 m ? 16 ga 4.0 m ? 14 ga 2.5 m ? 12 ga 1.6 m ? incorporation of a 100fd capacitor at the input terminals is recommended as compensation for the dynamic effects of the parasitic resistance of the input cable reacting with the complex impedance of the converter input, and to provide an energy reservoir for transient input current requirements. figure vi. problems of parasitic resistance in input leads vin rtn case enable 1 sync out sync in r p r p i rtn i in e source system ground e rtn 100 fd as an example of the effects of parasitic resistance, consider an afl2815d operating at full power of 100w. from the specification sheet, this device has a minimum efficiency of 83% which represents an input power of more than 120w. if we consider the case where line voltage is at its? minimum of 16v, the steady state input current necessary for this example will be slightly greater than 7.5a. if this device were connected to a voltage source with 10 feet of 20 gauge wire, the round trip (input and return) would result in 0.2 ? of resistance and 1.5v of drop from the source to the converter. to assure 16v at the input, a source closer to 18v would be required. in applications using the paralleling option, this drop will be multiplied by the number of paralleled devices. by choosing 14 or 16 gauge wire in this example, the parasitic resistance and resulting voltage drop will be reduced to 25% or 31% of that with 20 gauge wire. another potential problem resulting from parasitically induced voltage drop on the input lines is with regard to the operation of the enable 1 port. the minimum and maximum operating levels required to operate this port are specified with respect to the input common return line at the converter. if a logic signal is generated with respect to a ?common? that is distant from the converter, the effects of the voltage drop over the return line must be considered when establishing the worst case ttl switching levels. these drops will effectively impart a shift to the logic levels. in figure vi, it can be seen that referred to system ground, the voltage on the input return pin is given by e rtn = i rtn ? r p therefore, the logic signal level generated in the system must be capable of a ttl logic high plus sufficient additional amplitude to overcome e rtn . when the converter is inhibited, i rtn diminishes to near zero and e rtn will then be at system ground.
10 www.irf.com afl28xxd series mechanical outlines case x case w pin variation of case y 1.260 1.500 2.500 2.760 3.000 ? 0.128 0.250 1.000 ref 0.200 typ non-cum 0.050 0.220 pin ? 0.040 0.238 max 0.380 max 2.975 max 1 6 7 12 0.050 0.220 0.250 1.000 pin ? 0.040 0.525 0.380 max 2.800 0.42 case y case z pin variation of case y 1.500 1.750 2.500 0.25 typ 1.150 0.050 0.220 1 6 7 12 1.750 0.375 2.00 0.250 1.000 ref 0.200 typ non-cum pin ? 0.040 0.300 ? 0.140 0.238 max 0.380 max 2.975 max 0.050 0.220 0.250 1.000 ref pin ? 0.040 0.525 0.380 max 2.800 0.36 ber yllia w arning : these converters are hermetically sealed; however they contain beo substrates and should not be ground or subjected to any o ther operations including exposure to acids, which may produce beryllium dust or fumes containing beryllium tolerances, unless otherwise specified: .xx = 0.010 .xxx = 0.005
www.irf.com 11 afl28xxd series pin designation pin # designation 1 + input 2 input return 3 case ground 4 enable 1 5 sync output 6 sync input 7 + output 8 output return 9 - output 10 output voltage trim 11 share 12 enable 2 standard microcircuit drawing equivalence table standard microcircuit ir standard drawing number part number 5962-95795 afl2805d 5962-95796 afl2812d 5962-94724 afl2815d
12 www.irf.com afl28xxd series part numbering world headquarters: 233 kansas st., el segundo, california 90245, tel: (310) 322 3331 ir santa clara: 2270 martin av., santa clara, california 95050, tel: (408) 727-0500 visit us at www.irf.com for sales contact information . data and specifications subject to change without notice. 12/2006 notes: best commercial practice sample tests at low and high temperatures -55c to +105c for ahe, ato, atw device screening requirement mil-std-883 method no suffix es hb ch temperature range -20c to +85c -55c to +125c -55c to +125c -55c to +125c element evaluation mil-prf-38534 n/a n/a n/a class h non-destructive bond pull internal visual 2017 yes yes yes temperature cycle 1010 n/a cond b cond c cond c constant acceleration 2001, y1 axis n/a 500 gs 3000 gs 3000 gs pind 2020 n/a n/a n/a n/a burn-in 1015 n/a 48 hrs@hi temp 160 hrs@125c 160 hrs@125c final electrical mil-prf-38534 25c 25c -55c, +25c, -55c, +25c, ( group a ) & specification +125c +125c pda mil-prf-38534 n/a n/a n/a 10% seal, fine and gross 1014 cond a cond a, c cond a, c cond a, c radiographic 2012 n/a n/a n/a n/a external visual 2009 yes yes yes n/a n/a 2023 n/a n/a afl 28 05 d x /ch model input voltage 28 = 28v 50 = 50v 120 = 120v 270 = 270v output voltage output d = dual case style w, x, y, z screening level (please refer to screening table) no suffix, es, hb, ch 05 = 5v 12 = 12v 15 = 15v

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